Integrated circuits and their physical packaging are described by physical designs in the form of 2-dimensional geometric models. The increasing data volume accomplished by the increasing complexity of these designs is becoming a significant problem for engineering design automation, since it overstresses the software design tools which, in turn, impact the design cycle time, design cost and time to market.
Physical design data is analyzed many times to verify that physical mask constraints are not exceeded, electrical performance is satisfactory, and the physical design implements the logical design intent. For example, it is often necessary to determine wide or fat portions of material in a very large scale integrated (VLSI) semiconductor mask layout for the purposes of design rule checking (DRC), data preparation prior to mask build and the like. This determination is problematic with modern tools because the area around the base shape or cell which must be searched is large causing the effective flattening of the layout many times over. Thus, vast CPU and memory resources are consumed in the process and often for little real value.
The standard approach to managing design complexity has been to optimize the design itself, but verify, or check the design in flattened form. However, the computation of the high level representation of the physical partitions can be a significant problem when the data volume in a partition is substantial. Moreover, any attempt to break the hierarchical design constraints using ad-hoc design fixes invalidates the integrity of the partitioning and reduces the verification process to a completely flat analysis problem. Finally, the methodology constraints typically prevent the designer from fully exploiting the available density offered by the physical design technology.
Thus, DRC tools are validated using flat designs with little or no hierarchy test cases because hierarchy test cases must be developed manually. Due to the time requirements for developing a complete set of hierarchy test cases, hierarchy test cases are not very practical and tend not to be used to verify DRC programs. Thus, there is a need for an automated method of generating valid test cases for more coverage in DRC tool validation.